A layout advisor for timing-critical bus routing

Wei Huang, A. Kahng
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引用次数: 3

Abstract

We describe a "topology advisor" for routing of critical (multisource) buses in building-block design. The tool accepts as input a block layout, a two-layer routing cost structure superposed over the block layout, terminal locations for a multi-source bus, and source-sink delay upper bound (linear or Elmore delay) constraints for all terminal pairs. The b best routing solutions (b a user parameter) that satisfy all constraints are returned. Efficient implementations of exhaustive search are used to guarantee optimal results when practical, and otherwise yield fast, high-quality results (if the problem is large or if the constraints are loose). Practical features include: (i) modeling of per-region and per-layer routing costs, (ii) routing to terminals located inside blocks, (iii) optional splitting of k-pin bus routes when the optimal routing passes through narrow channels, and (iv) heuristic speedups based on clustering and sampling.
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用于定时关键总线路由的布局建议器
我们描述了构建块设计中用于关键(多源)总线路由的“拓扑顾问”。该工具接受作为输入的块布局,叠加在块布局上的两层路由成本结构,多源总线的终端位置,以及所有终端对的源接收器延迟上限(线性或Elmore延迟)约束。返回满足所有约束的b个最佳路由解决方案(b为用户参数)。穷举搜索的高效实现用于保证实际情况下的最优结果,并在其他情况下产生快速、高质量的结果(如果问题很大或约束很松散)。实际功能包括:(i)每个区域和每层路由成本的建模,(ii)路由到位于块内的终端,(iii)当最佳路由通过狭窄通道时k-pin总线路线的可选分裂,以及(iv)基于聚类和抽样的启发式加速。
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