A Dynamic Scan Chain Reordering for Low-Power VLSI Testing

Abstract

Low-power electronic circuit design for VLSI (Very Large Scale Integrated) testing is one of key design issues since power consumption is increased dramatically during test operations due to heavy transitions. Scan chain reordering has been one of the efficient low-power test technology to solve this problem. In this paper, we propose a new dynamic scan cell reordering technique that improves power reduction ratios of the traditional static reordering of scan cells. This technique is simple to implement, and can be easily applied to several scan chain based test circuits. Experimental results show that the proposed method can reduce power by up to 23% and 15% of the maximum and average power consumption for ITC99 benchmark circuits.