A cost-effective pre-bond functional test architecture for 3D SoCs

Abstract

We proposed a novel pre-bond functional test architecture for core-level partitioned 3D SoCs. In this test architecture, a new test access mechanism is built by probing functional Through Silicon Vias (TSVs) and by linking functional TSVs to all pins of IP cores under test. In order to reduce the Design-for-Test (DfT) cost, we propose a novel scheme to share the functional TSVs among pins of IP cores and reuse wires which connect pins to the same functional TSVs. Experimental results based on the MCNC benchmarks circuits demonstrate the feasibility and effectiveness of the DfT optimization methods.