P. Zuchowski, J. H. Panner, D. Stout, J. Adams, F. Chan, P. Dunn, A. D. Huber, J. J. Oler
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引用次数: 11
Abstract
This paper discusses a design style that utilizes an area array of flip-chip solder bump connections, I/O circuit designs that implement a programmable impedance matching algorithm, and a design system that must utilize these features during chip layout, chip checking, and release to manufacturing. Results from a recent test chip are also given.
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