Power estimation technique for deep submicrometer conventional MOS transistors

Abstract

In this paper, we present a power macromodeling technique for transistor level. The proposed technique is used to estimate the power dissipation on conventional metal-oxide-semiconductor (MOS) transistors. As the dynamic power is directly linked with the load capacitance (CL), it is also a lumped capacitance of all internal parasitic capacitances. In our model, we take an account of the parasitic capacitances with their dependence on channel width and the length. Suitable values of other factors (i.e. threshold voltage VT, gate voltage VGS, drain voltage VDD etc.) are used for the power consumption of the MOS transistors. The Preliminary results are effective and our macromodel provides the accurate power estimation.