An Inner Round Pipeline Architecture Hardware Core for AES

Abstract

The following article presents an inner round architecture for the AES Encryption Scheme suitable for implementation on FPGAs and as ASICs. The uniformity between the encryption and decryption hardware makes them suitable for implementation as separate or co-existing blocks as required. The modular approach of our architecture allows for different encryption/decryption core configurations providing a compact, scalable implementation that is suitable for applications that may demand compact yet high performant hardware. The architecture employs a combinational S-Box forming a crucial step in the parallel operation of the hardware. For an operating frequency of 278.5 MHz, the hardware achieves a high throughput of about 3.5 gigabits per second (GBps).