Impact and compensation of dead time on common mode voltage elimination modulation for neutral-point-clamped three-phase inverters

Abstract

This paper presents a detailed analysis on the impact of dead time (DT) on the EMI performance of three-level neutral-point-clamping (3L-NPC) inverters with Common Mode Elimination (CME) modulation. The implementation method of CME modulation is presented and the benefits and drawbacks are discussed which shows that the benefit of CME modulation is highly related with the DT added to the system and make it less practical in a real system. By analyzing the switching states of one phase leg, the impacts of DT on CM voltage are discussed in detail. Based on this analysis, a DT compensation method for CME modulations is proposed, where the position of the compensated pulses need to be considered carefully to achieve both CM voltage reduction and the current distortion minimization. Both simulation and experimental verification are implemented to verify the analysis based on a 2.5 kW prototype and the results match well with the analysis and verify the proposed method.