{"title":"Error resilience in nano-electronic digital circuits and systems","authors":"H. Vierhaus","doi":"10.1109/SPA.2015.7365102","DOIUrl":null,"url":null,"abstract":"For more than 10 years, many authors have predicted dependability problems with large-scale integrated circuits, implemented in nano-technologies. Reasons are new and enhanced fault mechanisms that affect either a higher vulnerability against transient faults, caused by particle radiation, or pre-mature aging due to device degradation. More recently, power dissipation on ICs has become a major problem, also affecting reliability aspects, since most fault mechanisms are strongly enhanced by higher temperatures. The final challenge is to handle a variety of fault effects at minimum cost in extra hardware in order to enhance dependability and system life time. The tutorial first gives an introduction into the basic problems. Next methods for the detection and correction of short transient faults are shown. Then methods that can detect and correct delay faults are presented, followed by new architectures that may handle transient faults and delay faults in combination. Built-in self repair (BISR) is presented as a method that is not capable of on-line error correction, but may be helpful for life-time extension. Finally there is a comparison of such technologies in terms of requirements for extra time or extra power.","PeriodicalId":423880,"journal":{"name":"2015 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPA.2015.7365102","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
For more than 10 years, many authors have predicted dependability problems with large-scale integrated circuits, implemented in nano-technologies. Reasons are new and enhanced fault mechanisms that affect either a higher vulnerability against transient faults, caused by particle radiation, or pre-mature aging due to device degradation. More recently, power dissipation on ICs has become a major problem, also affecting reliability aspects, since most fault mechanisms are strongly enhanced by higher temperatures. The final challenge is to handle a variety of fault effects at minimum cost in extra hardware in order to enhance dependability and system life time. The tutorial first gives an introduction into the basic problems. Next methods for the detection and correction of short transient faults are shown. Then methods that can detect and correct delay faults are presented, followed by new architectures that may handle transient faults and delay faults in combination. Built-in self repair (BISR) is presented as a method that is not capable of on-line error correction, but may be helpful for life-time extension. Finally there is a comparison of such technologies in terms of requirements for extra time or extra power.