Using Machine Learning to Estimate Utilization and Throughput for OpenCL-Based Matrix-Vector Multiplication (MVM)

Abstract

OpenCL is a framework for writing programs that execute across heterogeneous platforms, including FPGAs. OpenCL allows users to write standardized C-like code for the host as well as for the hardware accelerators, thus reducing the programming challenge for FPGAs. Hardware descriptions can be written in OpenCL using different memory access and data partitioning strategies. Matrix-Vector Multiplication (MVM) is the critical computational bottleneck for many System of Linear Equations (SLEs) solvers. The MVM OpenCL kernel can be optimized by varying several design parameters in the OpenCL description, improving hardware performance. To effectively explore the design space, logic synthesis is performed after each iteration of setting design parameters to determine their impact on design area and performance. However, each of these synthesis runs can take multiple hours. Hence, manual design space exploration for a large number of designs is prohibitive. To address this challenge, a prediction of FPGA utilization and throughput can significantly reduce the design time. This paper presents a machine learning-based approach to estimating FPGA utilization and throughput for a given set of design parameter values. It also presents an optimized MVM implementation obtained after compiling, synthesizing, and executing over 100 designs. The Random Forest machine learning algorithm estimates the result and for 175 designs, the average error is. 0098%,. 0012%,. 0039%,. 0414%, and 123.21% for estimating Look-up Tables (LUTs), Digital Signal Processors (DSPs), memory bits, RAM blocks and throughput (GFLOPs) respectively.