Impact of reconfiguration logic on the optimization of defect-tolerant integrated circuits

Abstract

Two aspects of the impact of reconfiguration logic on the optimization of defect-tolerant integrated circuits (ICs) are analyzed. An important consequence to design decisions of neglecting reconfiguration logic is presented. Expressions are developed to predict the number of transistors necessary to implement the reconfiguration logic of a simple defect-tolerance strategy using CMOS technology. The results show that neglecting this reconfiguration logic can lead to inappropriate design decisions. An example of a fine-grain logic array is presented to demonstrate the latter conclusion.<>