VLSI implementation of a reconfigurable cellular neural network containing local logic (CNNL)

IEEE International Workshop on Cellular Neural Networks and their Applications Pub Date : 1990-12-16 DOI:10.1109/CNNA.1990.207526

K. Halonen, V. Porra, T. Roska, L. Chua

引用次数: 38

Abstract

A new integrated circuit cellular neural network implementation having digitally or continuously selectable template coefficients is presented. Local logic and memory is added into each cell providing a simple dual computing structure (analog and digital). The variable-gain operational transconductance amplifier (OTA) is used as voltage controlled current sources to program the weighting factors of the template elements. A 4-by-4 CNN circuit is realized using the 2 mu m analog CMOS-process. The circuit with different template configurations has been simulated with HSPIC.<>

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包含局部逻辑(CNNL)的可重构细胞神经网络的VLSI实现

提出了一种新的集成电路细胞神经网络实现，具有数字或连续可选的模板系数。本地逻辑和存储器被添加到每个单元，提供一个简单的双计算结构(模拟和数字)。采用变增益运算跨导放大器(OTA)作为压控电流源，对模板元件的权重因子进行编程。采用2 μ m模拟cmos工艺实现了一个4 × 4的CNN电路。用HSPIC对不同模板配置下的电路进行了仿真。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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IEEE International Workshop on Cellular Neural Networks and their Applications

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