A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS

Abstract

We propose design techniques that enable the realization of power-efficient single-bit CT-ΔΣ ADCs at multi-Gb/s speeds. An FIR DAC [1 ] is used to reduce sensitivity to clock jitter and relax loop filter linearity. A mostly analog path compensates the modulator for the delay introduced by the FIR DAC. The CTDSM samples at 3.6GS/S, has 83dB DR in 36MHz BW, and occupies 0.12mm2 in 90nm CMOS. Dissipating 15mW from a 1.2V supply, it thereby achieves an FoMSNDR of 72.8fJ/level, which is an improvement over the state of the art for converters with bandwidths greater than 20MHz.