Power-area efficient VLSI implementation of decision tree based spike classification for neural recording implants

Abstract

Spike classification is the last step in spike sorting to reduce the data rate of a brain-machine interface. This paper presents a new decision tree based spike classification method that achieves a classification accuracy comparable to methods based on L1 distance. The design was synthesized for 130nm CMOS with an architecture that interleaves eight channels to optimize the power-area tradeoff. Resource analysis shows that the resulting design consumes 32nW of power per channel at a clock rate of 50KHz and occupies 5115μm2 of area per channel.