Low-power CMOS on-chip voltage reference using MOS PTAT: an EP approach

Abstract

This paper presents a new low-power on-chip voltage reference less sensitive to the process variation in an 0.5 /spl mu/m DRAM process where neither reliable BJT nor depletion MOS are available. The proposed voltage reference uses the MOS threshold voltage and a PTAT (proportional to the absolute temperature) voltage generated only from MOS transistors, and achieves considerably good performance at the total current of less than 8 /spl mu/A with an external power supply voltage ranging from 2.8 to 4 V. The measured temperature coefficient is about 360 ppm//spl deg/C at temperatures ranging from 0/spl deg/C to 100/spl deg/C. In addition, an optimization technique is proposed to find a set of optimal parameters in designing circuits.