Optimizing Storage Performance with Calibrated Interrupts

Amy Tai, I. Smolyar, M. Wei, Dan Tsafrir
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引用次数: 11

Abstract

After request completion, an I/O device must decide whether to minimize latency by immediately firing an interrupt or to optimize for throughput by delaying the interrupt, anticipating that more requests will complete soon and help amortize the interrupt cost. Devices employ adaptive interrupt coalescing heuristics that try to balance between these opposing goals. Unfortunately, because devices lack the semantic information about which I/O requests are latency-sensitive, these heuristics can sometimes lead to disastrous results. Instead, we propose addressing the root cause of the heuristics problem by allowing software to explicitly specify to the device if submitted requests are latency-sensitive. The device then “calibrates” its interrupts to completions of latency-sensitive requests. We focus on NVMe storage devices and show that it is natural to express these semantics in the kernel and the application and only requires a modest two-bit change to the device interface. Calibrated interrupts increase throughput by up to 35%, reduce CPU consumption by as much as 30%, and achieve up to 37% lower latency when interrupts are coalesced.
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通过校准中断优化存储性能
请求完成后,I/O设备必须决定是通过立即触发中断来最小化延迟,还是通过延迟中断来优化吞吐量,预计更多的请求将很快完成,并帮助分摊中断成本。设备采用自适应中断合并启发式,试图在这些相反的目标之间取得平衡。不幸的是,由于设备缺乏关于哪些I/O请求对延迟敏感的语义信息,这些启发式方法有时会导致灾难性的结果。相反,我们建议通过允许软件显式地指定设备提交的请求是否对延迟敏感来解决启发式问题的根本原因。然后,设备“校准”其中断,以完成对延迟敏感的请求。我们将重点讨论NVMe存储设备,并说明在内核和应用程序中表达这些语义是很自然的,并且只需要对设备接口进行适度的两位更改。校准后的中断可将吞吐量提高35%,将CPU消耗降低30%,并在合并中断时将延迟降低37%。
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