Performance Reduction For Automatic Development of Parallel Applications For Reconfigurable Computer Systems

Abstract

In the paper, we review a suboptimal methodology of mapping of a task information graph  on the architecture of a reconfigurable computer system. Using performance reduction methods,  we can solve computational problems which need hardware costs exceeding the available hardware  resource. We proved theorems, concerning properties of sequential reductions. In our case, we have  the following types of reduction such as the reduction by number of basic subgraphs, by number  of computing devices, and by data width. On the base of the proved theorems and corollaries,  we developed the methodology of reduction transformations of a task information graph for its  automatic adaptation to the architecture of a reconfigurable computer system. We estimated the  maximum number of transformations, which, according to the suggested methodology, are needed  for balanced reduction of the performance and hardware costs of applications for reconfigurable  computer systems.