A Buffered Crossbar-Based Chip Interconnection Architecture Supporting Quality of Service

Abstract

As systems-on-a-chip (SoCs) become larger, the problem of interconnecting the various subsystems becomes more complicated. In this framework, certain alternatives to the standard busses, based on network technologies, have emerged as an innovative approach for future SoC interconnect. One of the main advantages of such an alternative, is that it can offer certain quality of service (QoS) over the internal cross-connects while at the same time it supports higher transfer rates than the existing on-chip busses. This paper presents a chip interconnection architecture, which is based on a buffered crossbar switch. The main advantage of the proposed system is that it efficiently supports different priority levels; it also provides several gigabits per second of aggregate bandwidth, while it introduces very low latency. Moreover, its hardware complexity is minimal. All those facts make this framework ideal for SoCs that contain IP cores with diverse speed/throughput requirements.