On The Implementation of Densely Packed Decimal Number System Based Adder: Prospects and Challenges

Abstract

Decimal digit number computation, through bit compression methodology, offers space and time saving, which can be incurred by the Chen-Ho and Densely Packed Decimal (DPD) coding techniques. Such coding techniques have a property of bit compression, like, three decimal digits can be represented by 10 bits instead of 12 bits in binary coded decimal (BCD) format. The compression has been obtained through the elimination of the redundant 0’s from BCD representation. This manuscript reports the pros and cons of the techniques mentioned above. The logic level functionalities have been examined through MATLAB, whereas circuit simulation has been erified through Cadence Spectre. Performance parameters (such as delay, power consumption) have been evaluated through CMOS gpdk45 nm technology. Furthermore, the best design has been chosen from them, and the decimal adder design technique has been incorporated in this paper.