Secure scan chain using a phase locking authentication technique

Abstract

Scan is a widely used DfT (Design for Testing) technique for digital circuits, which provides a high observability and controllability. However, scan architectures can be used as a powerful tool to attack integrated circuits and extract sensitive information stored in the hardware. With the advent of 3D stacked ICs, it has become essential to implement a robust security measure to prevent scan-based attacks. In this work, a phase locking solution is presented to secure the scan architecture. A Phase Locked Loop (PLL) is utilized to authenticate the tester and provide access to the scan chain. The proposed scheme is dynamic and supports different authentication requirements for different layers in a 3D stacked IC without increasing the area overhead.