{"title":"High Performance Crypto for 5G Wireless on x86 Platform","authors":"Liheng Zhang, Yao Dong","doi":"10.1109/ICPICS55264.2022.9873766","DOIUrl":null,"url":null,"abstract":"The crypto, including ciphering and integrity protection, is a high cycle consumption job inside PDCP in 5G. When 5G RAN is deployed on Cloud and Edge based on general x86 platform, there are two common ways to implement the crypto functions, namely software lib based or hardware acceleration QAT based. The former occupies computing resource, but is quick for small packets, while the latter saves computing resource, but has longer processing latency. Both of them may meet the performance scaling issue, as the packet size varies, especially when eMBB slice and uRLLC slice are both enabled. This paper provides an efficient way to have both high computation performance and low processing latency for crypto functions with Intel Architecture technologies.","PeriodicalId":257180,"journal":{"name":"2022 IEEE 4th International Conference on Power, Intelligent Computing and Systems (ICPICS)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE 4th International Conference on Power, Intelligent Computing and Systems (ICPICS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICPICS55264.2022.9873766","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The crypto, including ciphering and integrity protection, is a high cycle consumption job inside PDCP in 5G. When 5G RAN is deployed on Cloud and Edge based on general x86 platform, there are two common ways to implement the crypto functions, namely software lib based or hardware acceleration QAT based. The former occupies computing resource, but is quick for small packets, while the latter saves computing resource, but has longer processing latency. Both of them may meet the performance scaling issue, as the packet size varies, especially when eMBB slice and uRLLC slice are both enabled. This paper provides an efficient way to have both high computation performance and low processing latency for crypto functions with Intel Architecture technologies.