A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices

Abstract

Long reconfiguration times form a major bottleneck in dynamic reconfigurable systems. Many approaches have been proposed to address this problem. However, improvements in the configuration circuit that introduces this overhead are usually not considered. The high reconfiguration times are due to the large amount of configuration bits sent through a constrained data path. In order to alleviate this, we propose a novel FPGA configuration circuit architecture to speedup bitstream (re)configuration and relocation. Experimental results using the MCNC benchmark set indicate that our proposal reconfigures 4 times faster and relocates 19.8 times more efficient compared to the state of the art approaches. This is achieved by transporting only the data required for the configuration in flight and by avoiding external communication while relocating. Moreover, the configuration bitstream sizes of the evaluated benchmarks are reduced by 65%on average. In addition, our proposal introduces negligible hardware and communication protocol overheads.