Improving Flash Translation Layer Performance by Using Log Block Mapping Scheme and Two-level Buffer for Address Translation Information

Abstract

In the era of big data, the requirement of mass storage and fast access of data makes solid state disk(SSD) based on NAND flash be widely used. However, increasing flash memory capacity imposes huge SRAM consumption for logical-physical translation table in a page-level flash translation layer(FTL). Existing FTL schemes selectively cache the on-demand address mappings to quicken the address translation, while keeping all address mappings in flash memory. But the page-level catching mechanism causes a certain degree of cache pollution. In this paper, we manage page-level address translation information at hybrid-level mapping scheme and use two-level buffer for map groups to decrease SRAM consumption while reducing the cache pollution. What's more, an efficient replacement policy is designed. We can increase the cache hit ratio and reduce the write backs of evicted dirty entries and decrease garbage collection operations by these means. The performance and lifetime of the flash memory is improved. Experimental results show that the proposed scheme increases cache hit ratio by up to 28% and decreases the average response time by up to 23% compared with the existing FTL schemes.