InAs gate-all-around nanowire MOSFETs by top-down approach

Abstract

InAs gate-all-around (GAA) nanowire MOSFETs are experimentally demonstrated for the first time by a top-down approach ^[1-3]. Thanks to the well-controlled nanowire release process and the novel ALD high-k/metal gate stack process, InAs nFETs with channel length (L_ch) ranging from 380 to 20 nm and nanowire width (W_NW) from 60 to 20 nm are achieved. With an EOT of 3.9 nm, high drain current of 4.3 A/mm at V_ds = V_gs = 2 V and maximum transconductance (g_max) of 1.6 S/mm at V_ds = 1 V are obtained in a device with W_NW = 20 nm and L_ch = 180 nm, normalized by the perimeter of the nanowires. A detailed scalability study (V_TH, g_m, I_ds vs. L_ch) was carried out. The devices in this study show strong dependence on the nanowire width and smaller nanowire size offers much enhanced electrical performance and better immunity from the short channel effects (SCEs).