Operating principle verification and scaling benefits of SGLC eNVM

Abstract

The authors demonstrated and verified the operation of a SGLC eNVM cell using 3D and 2D TCAD simulations. In addition, we have explained the benefits of the SGLC NVM cell as CMOS process design rules shrink. The novel SGLC cell shows a smaller size than 6T SRAM for beyond the 65 nm technology node. The SGLC cell shows ideal characteristics for eNVM, such as a fast program speed, multi-time programmable support, over-erase free features as well as an SRAM comparable cell size without any additional process steps.