Dynamic response optimization of the synthetic ripple modulator for a point-of-load converter with adaptive voltage positioning

Abstract

Modern computation and communication integrated circuit are continually powered from a lower voltage with stringent static and dynamic limitations. The power supplies with hysteretic modulators exhibit superior dynamic performance and help reduce the number of output capacitors without sacrificing transient response. The synthetic ripple modulator (SRM) allows proper hysteretic operation even with a small and corrupted output voltage ripple. This paper discusses a dynamic optimization technique for the SRM, which enables the voltage regulator module (VRM) to get back within regulation in the least amount of time with minimum number of output capacitors. The design methodology and corresponding equations are derived and verified with a design example. Experimental validation on a 1.8 V/15 A module demonstrates the effectiveness of the technique with a maximum excursion time of 5 µs above the static regulation limits.