Design of Low Power P-Gated Schmitt Trigger SRAM in 65nm CMOS Technology

Abstract

The trend of faster microprocessors at lower supply voltages demanded the need for a stable and less power consuming SRAM. This study answered these issues by implementing a 12T Power Gated Schmitt Trigger SRAM implemented in Full Custom 65nm CMOS technology. The read and write stability was accomplished without extra peripheral circuitry with more control signals per cell. The design schematic, layout, and results were obtained using SYNOPSYS Custom Designer. The Full Custom design resulted to 1.25 sq. mm. chip area, 2.43 mW power consumption, and 31.45 ns slack time. Results also show that most power consumption from the Full Custom design come from the banking and row decoders. The memory array has a 16-bit addressable word line, 512 byte memory capacity, simulated with 25–200 MHz operating frequency and under 1V supply voltage.