Incorporating self-testing capabilities into a systolic array cell for digital signal processing

Abstract

Techniques for built-in self-test (BIST) are examined. They can be used to modify an existing systolic array controller chip and a multiplier/accumulator chip, called a systolic array cell, so that self-testing can be performed. The goal is to implement a systolic array cell which has self-test capabilities and can efficiently perform various signal processing algorithms such as multiplication, the fast Fourier transform, and convolution. BIST and how BIST can be used in a systolic array are examined. A 2D matrix multiplication algorithm is described. The effects on performance and hardware overhead of incorporating BIST in an array are described