Efficient parallel algorithms for search problems: applications in VLSI CAD

[1990 Proceedings] The Third Symposium on the Frontiers of Massively Parallel Computation Pub Date : 1990-10-08 DOI:10.1109/FMPC.1990.89455

S. Arvindam, V. Kumar, V. N. Rao

引用次数: 26

Abstract

Experimental results are presented to demonstrate that it is possible to speed up search-based algorithms by several orders of magnitude. Highly optimized sequential programs were first implemented in the C language for two applications: floor plan verification and tautology verification. Then parallel programs were developed for the Ncube by modifying the sequential programs to incorporate dynamic load balancing. The speedups obtained on 1024 processors ranged from 430 to 1099 for floor plan optimization, with larger problems showing higher speedups. For tautology verification the speedup on 1024 processors ranged from 564 to 1007, with larger problems again showing higher speedups.<>

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搜索问题的高效并行算法:在VLSI CAD中的应用

实验结果表明，可以将基于搜索的算法的速度提高几个数量级。高度优化的顺序程序首先在C语言中实现，用于两个应用程序:平面图验证和同义重复验证。在此基础上，通过对顺序程序的修改，引入动态负载均衡，开发了Ncube并行程序。对于平面图优化，在1024个处理器上获得的加速从430到1099不等，较大的问题显示出更高的速度。对于同义式验证，1024处理器的加速范围从564到1007，问题越大，速度也越快。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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[1990 Proceedings] The Third Symposium on the Frontiers of Massively Parallel Computation

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