Designing of FPGA based high performance 32 bit FFT processor with BIST

Abstract

Designing and implementation of 32 bit and 64 point pipelined FFT processor is presented in this paper. This FFT processor is going to be implemented on Field Programmable Gate Array (FPGA). The aim behind this is to reduce the number of cycles required for computation. The architecture of FFT has two pipelines. Out of this one pipeline is present in execution of the complex multiplication of butterfly unit and other is present in the RAM unit. In this architecture a novel simple address mapping scheme is proposed. The twiddle factor in this architecture is not going to be stored in ROM memory, it is going to be generated and accessed directly. The Built In Self Test (BIST) provided in this is used to design such technique which test itself.