{"title":"Current transport in graphene tunnel field effect transistor for RF integrated circuits","authors":"M. Fahad, A. Srivastava, A. Sharma, C. Mayberry","doi":"10.1109/IEEE-IWS.2013.6616800","DOIUrl":null,"url":null,"abstract":"In this work, an analytical current transport model of Graphene Nanoribbon (GNR) Tunnel Field Effect Transistor (T-FET) is presented considering drain source voltage (VDS), gate source voltage (VGS), carrier mobility (μ) and top gate dielectric (tOX). For a GNR width of 5nm at 0.275eV band gap, ON current of 1605 μA/μm is calculated with a very high ON/OFF current ratio of 107. Subthreshold slope of 7.07mV/decade is calculated from I-VGS transfer characteristics. Current saturation is observed for input voltage, VGS of 0.28V and beyond for varying VDS values. Performance of the proposed model is compared with the earlier published work and the projected 2011 ITRS MOSFET requirements and it is found that considering proper device geometry and input voltages, GNR T-FET can demonstrate seven times lower power dissipation and eight times higher intrinsic speed in the upper GHz range than in conventional CMOS technology.","PeriodicalId":344851,"journal":{"name":"2013 IEEE International Wireless Symposium (IWS)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Wireless Symposium (IWS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEEE-IWS.2013.6616800","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
In this work, an analytical current transport model of Graphene Nanoribbon (GNR) Tunnel Field Effect Transistor (T-FET) is presented considering drain source voltage (VDS), gate source voltage (VGS), carrier mobility (μ) and top gate dielectric (tOX). For a GNR width of 5nm at 0.275eV band gap, ON current of 1605 μA/μm is calculated with a very high ON/OFF current ratio of 107. Subthreshold slope of 7.07mV/decade is calculated from I-VGS transfer characteristics. Current saturation is observed for input voltage, VGS of 0.28V and beyond for varying VDS values. Performance of the proposed model is compared with the earlier published work and the projected 2011 ITRS MOSFET requirements and it is found that considering proper device geometry and input voltages, GNR T-FET can demonstrate seven times lower power dissipation and eight times higher intrinsic speed in the upper GHz range than in conventional CMOS technology.