{"title":"PANNE: a parallel computing engine for connectionist simulation","authors":"I.Z. Milosavlevich, B. Flower, M. Jabri","doi":"10.1109/MNNFS.1996.493816","DOIUrl":null,"url":null,"abstract":"PANNE (Parallel Artificial Neural Network Engine) is a parallel computing engine aimed at delivering super-computing power to numerical applications such as connectionist simulation and signal processing. The PANNE system exploits the features of the TMS320C40 DSP chip which make it suitable for building parallel computing systems. PANNE has been built with flexibility in mind; it is expandable in terms of hardware resources and supports both shared and distributed memory programming paradigms. We estimate that a system of 16 DSPs would be capable of delivering up to 80/spl times/10/sup 6/ connection updates per second.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"75 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MNNFS.1996.493816","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
PANNE (Parallel Artificial Neural Network Engine) is a parallel computing engine aimed at delivering super-computing power to numerical applications such as connectionist simulation and signal processing. The PANNE system exploits the features of the TMS320C40 DSP chip which make it suitable for building parallel computing systems. PANNE has been built with flexibility in mind; it is expandable in terms of hardware resources and supports both shared and distributed memory programming paradigms. We estimate that a system of 16 DSPs would be capable of delivering up to 80/spl times/10/sup 6/ connection updates per second.
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