Clutter Removal for Ground Penetrating Radars on FPGA: Design and Implementation

Abstract

The clutter encountered in Ground Penetrating Radar(GPR) systems is an important area of research since it decreases target detection rates. Real-time radar applications and hardware implementation of clutter removal methods in autonomous systems are crucial. In this study, robust non-negative matrix factorization (RNMF) is used, which requires simple mathematical operations and suitable for hardware implementations. FPGA was chosen as the hardware implementation environment due to its re-programmable feature. It has been shown that the hardware implementation results have the same performance as the clutter removal results obtained in the MATLAB environment.