Digitally assisted low-power pipelined analog-to-digital converters

Abstract

In this paper the main aspects in construction of the low-power CMOS pipelined analog-to-digital converters (ADCs) are discussed. The main requirements for a 1.5 bit redundant stage of the pipeline ADC are defined. Examples of the digital and the analog error correction mechanisms for the pipelined ADC in conjunction with the power reduction mechanisms are considered.