A 10 Gb/s low-power 4:1 multiplexer in 0.18 μm CMOS

Abstract

To reduce the power consumption, a 4:1 multiplexer using the CMOS logic is presented for high-speed operation. The proposed circuit adopts tree-type and half-rate structure. The CMOS logic, such as the dynamic CMOS and pseudo-static CMOS logic, is renewed in this design. The designed circuit is realized in a standard 0.18 μm CMOS process and uses 1.8 V supply voltage. The post simulated result shows that the fully integrated MUX operates well up to 10 Gb/s. The simulated eye opening is 200 mVpp on an external 50 Ohm load. The power consumption of the MUX is 53.3 mW at 10 Gb/s. The overall chip has a size of 0.575×0.475 mm2 and the core size is 0.18×0.12 mm2.