A FPGA based SAT solver with random variable selection

Abstract

SAT is one of the most important basic problems of many areas of computer science and control science. SAT solvers are software or hardware to solve an SAT instance. In this paper, an instance-specified SAT solver was developed with FPGA, which implements the DPLL algorithm with our innovative random variable selection. Moreover, we also introduced an innovative tool-chain of our SAT solver, which including two types of software, e.g., the Xilinx commercial software that is organized by our own C++ parser and some pieces of scripts, and a hardware of FPGA board. With the experiments, our solver keeps quite stable for the highest frequency (200MHz) of Vertex-7 FPGA board, the largest instance under testing has 200 variables and 1200 clauses with less than 3% resources consumed on the FPGA development board.