Suming You, Changchun Zhang, Fengbo Yuan, Yi Zhang, Ying Zhang
{"title":"A 65 nm CMOS Phase-locked Loop for 5G Mobile Communications","authors":"Suming You, Changchun Zhang, Fengbo Yuan, Yi Zhang, Ying Zhang","doi":"10.1109/PIERS-Fall48861.2019.9021850","DOIUrl":null,"url":null,"abstract":"A phase-locked loop (PLL) for multiphase clock generation for 5G Mobile Communications is presented in TSMC 65 nm CMOS technology. The PLL consists mainly of a phase/frequency detector (PFD), a charge pump (CP), and a voltage-controlled oscillator (VCO) with a third-order loop filter. The source-switching CP with a rail-to-rail operational amplifier is used to obtain perfect current matching, and the rotary traveling-wave VCO is employed for low phase noise, high oscillation frequency and multiphase clock generation. Simulation results show that, from a single voltage supply of 1.2 V, the PLL can achieve the frequency range of 24.1 ~ 27.6 GHz, the phase noise of 95.2 dBc/Hz@1 MHz from the output frequency of 25.6 GHz, and the total power of 58.3 mW is consumed.","PeriodicalId":197451,"journal":{"name":"2019 Photonics & Electromagnetics Research Symposium - Fall (PIERS - Fall)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Photonics & Electromagnetics Research Symposium - Fall (PIERS - Fall)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PIERS-Fall48861.2019.9021850","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A phase-locked loop (PLL) for multiphase clock generation for 5G Mobile Communications is presented in TSMC 65 nm CMOS technology. The PLL consists mainly of a phase/frequency detector (PFD), a charge pump (CP), and a voltage-controlled oscillator (VCO) with a third-order loop filter. The source-switching CP with a rail-to-rail operational amplifier is used to obtain perfect current matching, and the rotary traveling-wave VCO is employed for low phase noise, high oscillation frequency and multiphase clock generation. Simulation results show that, from a single voltage supply of 1.2 V, the PLL can achieve the frequency range of 24.1 ~ 27.6 GHz, the phase noise of 95.2 dBc/Hz@1 MHz from the output frequency of 25.6 GHz, and the total power of 58.3 mW is consumed.