{"title":"Design of data adaptive IFFT/FFT block for OFDM system","authors":"L. M. Rajeswari, S. Manocha","doi":"10.1109/INDCON.2011.6139435","DOIUrl":null,"url":null,"abstract":"Inverse Fast Fourier Transform/ Fast Fourier Transform (IFFT/FFT) processors are crucial blocks for an Orthogonal Frequency Division Multiplexing (OFDM) transceiver system. However, in the current OFDM systems, the system complexity and processing rate do not vary adaptively with the input data. In this paper, we propose a novel IFFT/FFT architecture for the OFDM Transceiver system that exploits the correlation between bytes of incoming information to adaptively choose between the Radix-2 and Radix • 4 algorithm. Using this architecture, we have achieved additional free data slots per frame. The transceiver system has been tested end-to-end and implemented on FPGA Board.","PeriodicalId":425080,"journal":{"name":"2011 Annual IEEE India Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Annual IEEE India Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/INDCON.2011.6139435","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
Inverse Fast Fourier Transform/ Fast Fourier Transform (IFFT/FFT) processors are crucial blocks for an Orthogonal Frequency Division Multiplexing (OFDM) transceiver system. However, in the current OFDM systems, the system complexity and processing rate do not vary adaptively with the input data. In this paper, we propose a novel IFFT/FFT architecture for the OFDM Transceiver system that exploits the correlation between bytes of incoming information to adaptively choose between the Radix-2 and Radix • 4 algorithm. Using this architecture, we have achieved additional free data slots per frame. The transceiver system has been tested end-to-end and implemented on FPGA Board.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
