Finding Glitches Using Formal Methods

2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) Pub Date : 2016-05-08 DOI:10.1109/ASYNC.2016.12

Yan Peng, I. W. Jones, M. Greenstreet

引用次数: 5

Abstract

The increasing scale and complexity of integrated circuits leads to many departures from a pure, synchronous design methodology. Clock-domain crossings, multi-cycle paths, and circuits for test with long combinational logic delays introduce vulnerabilities for glitch-related failures. Conventional simulation techniques can miss glitches because of the large number of value and timing scenarios. We have tried several commercially available tools but have not found a comprehensive solution. This paper presents a concise statement of what it means for a logic circuit to be "glitch free". This property can be verified using satisfiability solvers. We present our implementation using the ACL2 theorem proving system and some experimental results.

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使用形式化方法查找故障

集成电路的规模和复杂性的增加导致许多人偏离了纯粹的同步设计方法。时钟域交叉、多周期路径和具有长组合逻辑延迟的测试电路引入了与故障相关的漏洞。由于大量的值和时序场景，传统的仿真技术可能会忽略小故障。我们已经尝试了几种商业上可用的工具，但还没有找到一个全面的解决方案。本文给出了逻辑电路“无故障”的一个简明表述。这个性质可以用可满足性求解器来验证。给出了ACL2定理证明系统的实现和一些实验结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)

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