An automatic testing and diagnosis for FPGAs

Abstract

This paper presents a new design for testing and diagnosing the SRAM-based field programmable gate arrays (FPGA). By slightly modifying the original FPGA's SRAM memory, the new architecture permits the configuration data to be looped on a chip. Then the full testing and diagnosing of the FPGA are achieved by loading typically only one testing configuration datum (carefully chosen) instead of loading the total required configurations data (which is a very slow process) in the normal cases. Other configurations data are obtained by shifting the first one inside the chip. Consequently the test becomes faster. This method does not need a large outside memory (off-chip memory) for the test. The evaluation proves that this method becomes very interesting when the complexity of the configurable blocks (CLBs) or the chip size increase.