Integrating Drain Gating and Lector Techniques for Leakage Power Reduction in Ultra Deep Submicron Technology

Abstract

Due to scaling short channel effects are observed in devices under ultra deep submicron technology. The short channel effects causes leakage current to flow through the transistor which increases static power dissipation of the circuits. In this work two popular leakage reduction techniques namely drain gating technique and lector technique are combined to reduce the leakage power reduction of CMOS VLSI circuits. Different logic circuits are simulated using this novel combined technique for different input vectors. The performance of inverter and NOR gate are analyzed in terms of dc power dissipation and propagation delay and are compared with the existing popular leakage reduction techniques. Due to combined effect of drain gating and lector techniques, substantial reduction in leakage power is observed. The proposed technique reduces the leakage power consumption of Drain gating NOR gate by 44% and Lector NOR gate by 22% for 45nm technology.