Implementation of a Floating Point Adder and Subtracter in NoGAP, A Comparative Case Study

Abstract

Flexible Application Specific Instruction set Processors (ASIPs) are starting to replace monolithic ASICs in a wide variety of fields. However the construction of an ASIP is today associated with a substantial design effort. No GAP (Novel Generator of Micro Architecture and Processor) is a tool for ASIP design utilizing hardware multiplexed data paths. One of the main advantages of No GAP compared to other EDA tools for processor design, is that No GAP imposes few limits on the architecture and thus design freedom. To prove that No GAP can be used to design complex data paths a reimplementation of a floating point adder/subtracter previously implemented using Verilog with FPGA specific optimizations was reimplemented using the No GAP-CL. The adder/subtracter implemented in Verilog can operate at a frequency of 377 MHz in a Virtex-4SX35 (speed grade-12) as compared with the No GAP implementation which had a maximum operation frequency of 276 Mhz, using the hand optimized mantissa adder from the original Verilog code, the No GAP implementation reached timing closure at 326 Mhz.