{"title":"Architectural design simulation and silicon implementation of a very high fidelity decimation filter for sigma-delta data converters","authors":"I. Kale, R. Morling, A. Krukowski, D. A. Devine","doi":"10.1109/IMTC.1994.351969","DOIUrl":null,"url":null,"abstract":"This paper reports on results from the algorithmic design and simulation of a two-path poly-phase decimation filter with 24-bit accuracy over the frequency range from dc to approximately 16 kHz. The filter is suited for very high precision data conversion applications, and has been designed for use with a fourth-order /spl Sigmaspl Delta/ modulator running at 4096 kHz. This paper also reports on the fixed-point architectural design, comparative bit-level simulations and silicon implementation.<<ETX>>","PeriodicalId":231484,"journal":{"name":"Conference Proceedings. 10th Anniversary. IMTC/94. Advanced Technologies in I & M. 1994 IEEE Instrumentation and Measurement Technolgy Conference (Cat. No.94CH3424-9)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Proceedings. 10th Anniversary. IMTC/94. Advanced Technologies in I & M. 1994 IEEE Instrumentation and Measurement Technolgy Conference (Cat. No.94CH3424-9)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMTC.1994.351969","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
This paper reports on results from the algorithmic design and simulation of a two-path poly-phase decimation filter with 24-bit accuracy over the frequency range from dc to approximately 16 kHz. The filter is suited for very high precision data conversion applications, and has been designed for use with a fourth-order /spl Sigmaspl Delta/ modulator running at 4096 kHz. This paper also reports on the fixed-point architectural design, comparative bit-level simulations and silicon implementation.<>
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