{"title":"Application-specific coprocessor computer architecture","authors":"Y. Chu","doi":"10.1109/ASAP.1990.145500","DOIUrl":null,"url":null,"abstract":"The coprocessor computer architecture has a main processor and one or more coprocessors. The author proposes the use of the coprocessor computer architecture for realizing high-performance, application-specific parallel computers. The author presents a classification of coprocessor computer organization. Matching a coprocessor computer organization with a parallel algorithm is suggested. As an example, a lexical/parsing coprocessor, which can deliver tokens from lexical processing at the rate of one million per second and semantic-rule codes from parsing at the rate of 2.5 million per second is described. This coprocessor shortens compilation time, reduces compiler size, and lessens programmer effort. This result clearly shows the potential use of the coprocessor computer architecture for application-specific computers.<<ETX>>","PeriodicalId":438078,"journal":{"name":"[1990] Proceedings of the International Conference on Application Specific Array Processors","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1990] Proceedings of the International Conference on Application Specific Array Processors","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASAP.1990.145500","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
The coprocessor computer architecture has a main processor and one or more coprocessors. The author proposes the use of the coprocessor computer architecture for realizing high-performance, application-specific parallel computers. The author presents a classification of coprocessor computer organization. Matching a coprocessor computer organization with a parallel algorithm is suggested. As an example, a lexical/parsing coprocessor, which can deliver tokens from lexical processing at the rate of one million per second and semantic-rule codes from parsing at the rate of 2.5 million per second is described. This coprocessor shortens compilation time, reduces compiler size, and lessens programmer effort. This result clearly shows the potential use of the coprocessor computer architecture for application-specific computers.<>