Design quality tradeoff studies for 3D ICs built with nano-scale TSVs and devices

Abstract

Three dimensional integrated circuits (3D ICs) built with through-silicon vias (TSVs) have smaller footprint area, shorter wire-length, and better performance than 2D ICs. However, the quality of 3D ICs is strongly dependent on TSV dimensions and parasitics. Using large TSVs may cause silicon area overhead and reduce the amount of wirelength reduction in 3D ICs. In addition, non-negligible TSV parasitic capacitance can result in delay overhead affecting the delay of 3D ICs. Meanwhile, with the development of TSV manufacturing technology, nano-scale TSVs are emerging, which is expected to reduce the overheads caused by using large TSVs. Therefore, this paper investigates the impact of nano-scale TSVs on the quality of 3D ICs at future technology nodes. For this study, we develop a 16nm standard cell library, design 3D ICs using different process technologies (45nm, 22nm, and 16nm) and various TSVs diameters (from 5μm to 0.1μm), and discuss the impact of nano-scale TSVs.