Hardware architecture for 2D Gaussian filtering of HD images on resource constrained platforms

Abstract

A bi-dimensional filter for high accuracy image processing is implemented by using a novel partitioning method. The method is based on a number theory theorem, which permits to reduce the complexity of the operation to that of an adder chain and also the amount of the coefficients stored in memory, improving the memory organization. To show the advantage of such method, we implemented a Floating Point 32 (FP32) in hardware filtering applications and, in particular, for 2D FIR filters. Using Xilinx Virtex 7 Field Programmable Gate Array (FPGA) we obtain a critical path delay of 4.7ns which is comparable with the state-of-art.