An Architecture for Embedded IEEE 1588 Support

Abstract

This paper describes a first-generation architecture for IEEE 1588 support in an embedded processor. Close coupling is provided between the internal IEEE 1588 timebase and the packet interface in order to minimize the impact of software delays on the calculated time. A versatile timer interface is also directly coupled via hardware to the internal timebase. This allows direct programming of output events, including complex waveforms, from the internal timebase without software intervention.