Low Power Design of Edge Detector using Static Segmented Approximate Multipliers

Abstract

To avoid the carry resulting from the shortened component, this study suggests a truncation-based approximate multiplier with a compensation circuit created by selected k-map adjustments. Output error reduction and hardware trimming are accomplished concurrently. For error correction, 16x16 truncated multipliers based on approximate multipliers are created using streamlined NAND gate circuits. The computation process is enhanced to reduce the power, the original segmentation method for signed SSM is utilized and offer a simple, hardware-efficient corrective technique for verified multipliers. Verilog HDL is used to implement this design and Modelsim 6.4 c is used to simulate it. The synthesis process is done by Xilinx tool to measure the performance.