A 1.2V 23nm 6F2 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture

Abstract

We present a sensing scheme with local bitline sense amplifier (L-BLSA) for sub-1V DRAM core operation, which activates a low-Vt latch locally in time, the same as [1] but shares a common ground with a high-Vt latch. Hybrid LIO sense amplifier (H-LSA) is developed for robust LIO read operation at low voltage and high clock frequency. In order to reduce the die area, we develop a dummy-less 6F2 array architecture with no edge dummy array. These schemes are employed in a 1.2V 23nm 6F2 4Gb DDR3 SDRAM.