Multiple target performance evaluation model for HD video encoder VLSI architecture design

Abstract

FPGA and ASIC are suitable platforms for high definition video encoder implementation. Efficient video encoder VLSI architecture design suffers from several challenges and multiple target performance trade-off. Algorithm and hardware architecture are supposed to be jointly designed for multiple target performance trade-off. How to evaluate the performance, accounting for multiple target performance parameters, is one important problem for algorithm and architecture joint design. In this paper, we propose measure methods for multiple target performance parameters for VLSI architecture design, and then propose a novel multiple-target performance evaluation model. The performances of the prevalent H.264/AVC encoder architectures are evaluated with the proposed model. This work is meaningful for algorithm and architecture joint optimization.