Resonance-Based Power-Efficient Pulse Generator Design with Corresponding Distribution Network

Abstract

Pulsed-latches are treated as competing sequential elements to flip-flops, mainly for their low-power and high-performance advantages. In a typical pulsed-latch system, an explicit or implicit pulse generator (PG) is used to generate the necessary clock pulse, contributing a significant amount of power consumption. To address it, a novel resonance-based power-efficient PG circuit called RPG is proposed. A power reduction up to 60% and a more stable performance in variable temperature and voltage environments are shown in 12nm Fin-FET simulations as compared with other PG circuits in typical multi-bit applications. Furthermore, a distribution method of integrating RPG into traditional designs is provided. The evaluation in a test core shows that it achieves up to 21% in clock power reduction, with less clock skew overhead and no device area loss.